1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
In recent years, integrated circuits using an SOI (silicon on insulator) substrate instead of a bulk silicon wafer have been developed. By utilizing characteristics of a thin single crystal silicon layer formed over an insulating layer, transistors formed in the integrated circuit can be electrically separated from each other completely. Further, each transistor can be formed as a fully-depleted transistor, and thus a semiconductor integrated circuit with high added value such as high integration, high speed driving, and low power consumption can be realized. In the development of LSI using such an SOI substrate, improvement in operation frequency and processing capability is realized by reducing the area of a chip by using a multilayer wiring technique.
In recent years, a method for forming a single crystal silicon layer over a supporting substrate made of glass by using Smart Cut (registered trademark) has been proposed (e.g., see Reference 1: Japanese Published Patent Application No. H11-163363). Because a glass substrate has a larger area and is less expensive than a silicon wafer, when a glass substrate is used as a base substrate, an inexpensive large-area SOI substrate can be manufactured.
However, in the case where, after forming a transistor using a single crystal silicon layer over an insulating substrate such as glass, a wiring layer is provided over the transistor with an interlayer insulating layer interposed therebetween, miniaturization of the wiring layer is difficult because the planarity of the interlayer insulating layer is insufficient due to distortion of the substrate or the like.
In order to solve such difficulty of wiring miniaturization, a technique of manufacturing a miniaturized multilayer wiring below an SOI transistor by manufacturing the multilayer wiring prior to formation of the SOI transistor has been proposed (e.g., Reference 2: Japanese Published Patent Application No. 2003-110108).